A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards.
| Published in | Science Journal of Circuits, Systems and Signal Processing (Volume 2, Issue 2) |
| DOI | 10.11648/j.cssp.20130202.13 |
| Page(s) | 37-55 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2013. Published by Science Publishing Group |
Hardware Simulator, MIMO Radio Channel, FPGA, 802.11ac, LTE
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APA Style
Bachir Habib, Gheorghe Zaharia, Ghais El Zein. (2013). Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures. Science Journal of Circuits, Systems and Signal Processing, 2(2), 37-55. https://doi.org/10.11648/j.cssp.20130202.13
ACS Style
Bachir Habib; Gheorghe Zaharia; Ghais El Zein. Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures. Sci. J. Circuits Syst. Signal Process. 2013, 2(2), 37-55. doi: 10.11648/j.cssp.20130202.13
AMA Style
Bachir Habib, Gheorghe Zaharia, Ghais El Zein. Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures. Sci J Circuits Syst Signal Process. 2013;2(2):37-55. doi: 10.11648/j.cssp.20130202.13
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Download@article{10.11648/j.cssp.20130202.13,
author = {Bachir Habib and Gheorghe Zaharia and Ghais El Zein},
title = {Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures},
journal = {Science Journal of Circuits, Systems and Signal Processing},
volume = {2},
number = {2},
pages = {37-55},
doi = {10.11648/j.cssp.20130202.13},
url = {https://doi.org/10.11648/j.cssp.20130202.13},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20130202.13},
abstract = {A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards.},
year = {2013}
}
TY - JOUR T1 - Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures AU - Bachir Habib AU - Gheorghe Zaharia AU - Ghais El Zein Y1 - 2013/04/02 PY - 2013 N1 - https://doi.org/10.11648/j.cssp.20130202.13 DO - 10.11648/j.cssp.20130202.13 T2 - Science Journal of Circuits, Systems and Signal Processing JF - Science Journal of Circuits, Systems and Signal Processing JO - Science Journal of Circuits, Systems and Signal Processing SP - 37 EP - 55 PB - Science Publishing Group SN - 2326-9073 UR - https://doi.org/10.11648/j.cssp.20130202.13 AB - A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards. VL - 2 IS - 2 ER -
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